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  <div class="section" id="hwreg">
<span id="amdgpu-synid8-hwreg"></span><h1>hwreg<a class="headerlink" href="#hwreg" title="Permalink to this headline">¶</a></h1>
<p>Bits of a hardware register being accessed.</p>
<p>The bits of this operand have the following meaning:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 26%" />
<col style="width: 74%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Bits</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>5:0</p></td>
<td><p>Register <em>id</em>.</p></td>
</tr>
<tr class="row-odd"><td><p>10:6</p></td>
<td><p>First bit <em>offset</em> (0..31).</p></td>
</tr>
<tr class="row-even"><td><p>15:11</p></td>
<td><p><em>Size</em> in bits (1..32).</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>This operand may be specified as a positive 16-bit <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a> or using the syntax described below.</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 32%" />
<col style="width: 68%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Syntax</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>hwreg({0..63})</p></td>
<td><p>All bits of a register indicated by its <em>id</em>.</p></td>
</tr>
<tr class="row-odd"><td><p>hwreg(&lt;<em>name</em>&gt;)</p></td>
<td><p>All bits of a register indicated by its <em>name</em>.</p></td>
</tr>
<tr class="row-even"><td><p>hwreg({0..63}, {0..31}, {1..32})</p></td>
<td><p>Register bits indicated by register <em>id</em>, first bit <em>offset</em> and <em>size</em>.</p></td>
</tr>
<tr class="row-odd"><td><p>hwreg(&lt;<em>name</em>&gt;, {0..31}, {1..32})</p></td>
<td><p>Register bits indicated by register <em>name</em>, first bit <em>offset</em> and <em>size</em>.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Register <em>id</em>, <em>offset</em> and <em>size</em> must be specified as positive <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
<p>Defined register <em>names</em> include:</p>
<blockquote>
<div><table class="docutils align-default">
<colgroup>
<col style="width: 31%" />
<col style="width: 69%" />
</colgroup>
<thead>
<tr class="row-odd"><th class="head"><p>Name</p></th>
<th class="head"><p>Description</p></th>
</tr>
</thead>
<tbody>
<tr class="row-even"><td><p>HW_REG_MODE</p></td>
<td><p>Shader writeable mode bits.</p></td>
</tr>
<tr class="row-odd"><td><p>HW_REG_STATUS</p></td>
<td><p>Shader read-only status.</p></td>
</tr>
<tr class="row-even"><td><p>HW_REG_TRAPSTS</p></td>
<td><p>Trap status.</p></td>
</tr>
<tr class="row-odd"><td><p>HW_REG_HW_ID</p></td>
<td><p>Id of wave, simd, compute unit, etc.</p></td>
</tr>
<tr class="row-even"><td><p>HW_REG_GPR_ALLOC</p></td>
<td><p>Per-wave SGPR and VGPR allocation.</p></td>
</tr>
<tr class="row-odd"><td><p>HW_REG_LDS_ALLOC</p></td>
<td><p>Per-wave LDS allocation.</p></td>
</tr>
<tr class="row-even"><td><p>HW_REG_IB_STS</p></td>
<td><p>Counters of outstanding instructions.</p></td>
</tr>
</tbody>
</table>
</div></blockquote>
<p>Examples:</p>
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="mh">0x6</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">15</span><span class="p">)</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="mi">51</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">31</span><span class="p">)</span>
<span class="n">s_getreg_b32</span> <span class="n">s2</span><span class="p">,</span> <span class="n">hwreg</span><span class="p">(</span><span class="n">HW_REG_LDS_ALLOC</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">)</span>
</pre></div>
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